1. Field of the Invention
The present invention generally relates to semiconductor substrate processing systems. More specifically, the present invention relates to controlling etch processes in a semiconductor substrate processing system.
2. Description of the Related Art
To increase operational speed, devices (e.g., transistors, capacitors, and the like) in integrated microelectronic circuits have become ever smaller. The minimal dimensions of features of such devices are commonly called in the art, critical dimensions, or CDs. The CDs generally include the minimal widths of the features, such as lines, columns, openings, spaces between the lines, and the like.
One method of fabricating such features comprises forming a patterned mask (e.g., photoresist mask) on the material layer beneath such a mask (i.e., underlying layer) and then etching the material layer using the patterned mask as an etch mask.
The patterned masks are conventionally fabricated using a lithographic process when a pattern of the feature to be formed is optically transferred into a layer of photoresist. Then, the photoresist is developed, unexposed portions of the photoresist are removed, while the remaining photoresist forms a patterned mask.
An etch mask generally is, in a plan view, a replica of the feature to be formed (i.e., etched) in the underlying layer. As such, the etch mask comprises elements having same critical dimensions as the feature to be formed. Optical limitations of the lithographic process may not allow transferring a dimensionally accurate image of a feature into the photoresist layer when a CD of the element is smaller than optical resolution of the lithographic process.
To overcome limitations of the lithographic process, the photoresist mask may be fabricated using a two-step process. During a first step, the lithographic process is used to form the mask having elements that dimensions that are proportionally greater (i.e., scaled up) than the dimensions of the features to be formed. During a second step, such scaled-up elements are trimmed (i.e., isotropically etched) to the pre-determined dimensions. The trimmed photoresist mask is then used as an etch mask during etching the underlying material layer or layers.
Dimensional accuracy of the etch features generally defined by the corresponding elements of the trimmed photoresist mask. Manufacturing variables of the trimming process result in a broad statistical distribution (i.e., a large σ, where is σ a standard deviation) of the CDs within a group (i.e., batch) of the wafers. When such trimmed photoresist masks are used as the etch masks, critical dimensions of the etched features may be beyond an acceptable range for such dimensions, i.e., the features may be defective.
Therefore, there is a need in the art for an improved method and apparatus for controlling etch processes during fabrication of semiconductor devices in a semiconductor substrate processing system.